1. Field of the Invention
The present invention relates to semiconductor memories, and more particularly to high density nonvolatile semiconductor memories.
2. Description of the Related Art
Today's nonvolatile semiconductor memories require higher densities along with improvements in their performance and operation speed. A conventional nonvolatile semiconductor memory includes an array of memory cells each of which is comprised of a floating gate transistor having a floating gate, a control gate, a source and a drain. The memory cells are arranged in a matrix configuration of rows and columns. The control gates of the memory cells in a given row of memory cells are connected to the same one of a plurality of word lines. The drains of the memory cells in a given column of memory cells are connected to the same one of a plurality of bit lines. The memory cells, word lines and bit lines constitute a memory cell array. In order to improve an operation speed, data stored in the memory cells of a selected word line is simultaneously read out through the plurality of bit lines. Such a read operation is generally called a page read operation. The read-out data on the bit lines is temporarily stored in respective data latches generally called a page buffer. In a program operation, data input through data I/O pads or terminals is successively stored or loaded in the page buffer, and then the loaded data in the page buffer is thereafter programmed to the memory cells of a selected word line. Such a program operation is generally called a page program operation. These page read and page program operations are disclosed in the U.S. patent application Ser. No. 08/171,300, assigned to the present assignee. In order to perform the page read and page program operations, the data latches must be connected to respective bit lines. However, if the memory capacity of a nonvolatile semiconductor memory becomes higher without increasing the chip size or area, each of pitches or widths between adjacent bit lines should be reduced according to the increased memory capacity. Thus, there is a limitation in reducing the area occupied by the data latch connected to each bit line. Moreover, when employing a sense amplifier and data latch which are connected to each bit line in order to sense and store the data read out thereto, it is more difficult to reduce the pitch between all adjacent bit lines. Therefore, it is desirable to have a sophisticated layout that allows each of data latches and each of sense amplifiers to be placed between adjacent bit lines without increasing on-chip size or area.
Conventional nonvolatile semiconductor memories, such as electrically erasable and programmable read-only-memories (hereinafter referred to as an EEPROMs) with NAND structured cells, need large periods of time to sequentially store data from each data I/O terminal into corresponding data latches or to serially output data from data latches to a respective data I/O terminal. For example, a write cycle time, i.e. a time interval between the starts of successive data loading cycles from the data I/O terminals into the data latches, and a read cycle time, i.e. a time interval between the starts of successive read cycles from the data latches to the data I/O terminals, require about 80 nsec, respectively. Therefore, an EEPROM with high reliability and performance is needed which allows reduced data loading and read cycle times, using a reduced power supply voltage such as 3.3 volts.